module reg_128(
    input clk,
    input write,
    input [127:0]din,
    output [127:0]dout
);
    reg [127:0]doutt;
    always @(posedge clk) begin
       if(write)
            doutt <= din;
        else
            doutt <= doutt;
    end
    assign dout = doutt;

endmodule
   
